Uyemura, John P. <br/><br/>
Chip design for submicron VLSI CMOS layout and simulation 
by John P. Uyemura 
 - Toronto  Thomson/Nelson  2006 
 - xvi, 411p  ill.  24cm +1 CD-ROM (4 3/4 in.) 
<br/><br/> includes index p.407 - 411 
<br/><br/>Includes bibliographical references 
<br/><br/><label>ISBN: </label>053446629x 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits--Very large scale integration<br/>Metal oxide semiconductors, Complementary--Design and construction