TY  - BOOK
AU  - Ciletti, Michael D.
TI  - Modeling, Synthesis, And Rapid Prototyping With The Verilog HDL
SN  - 0139773983
PY  - 1999///
CY  - New Jersey
PB  - Prentice Hall
KW  - Verilog ( computer Hardware description language)
N1  - includes index : p. 710 - 724
ER  -