Chip design for submicron VLSI CMOS layout and simulation
Uyemura, John P.
Chip design for submicron VLSI CMOS layout and simulation by John P. Uyemura - Toronto Thomson/Nelson 2006 - xvi, 411p ill. 24cm +1 CD-ROM (4 3/4 in.)
includes index p.407 - 411
Includes bibliographical references
053446629x
Integrated circuits--Very large scale integration
Metal oxide semiconductors, Complementary--Design and construction
Chip design for submicron VLSI CMOS layout and simulation by John P. Uyemura - Toronto Thomson/Nelson 2006 - xvi, 411p ill. 24cm +1 CD-ROM (4 3/4 in.)
includes index p.407 - 411
Includes bibliographical references
053446629x
Integrated circuits--Very large scale integration
Metal oxide semiconductors, Complementary--Design and construction